1. Field of the Invention
The present invention generally relates to wiring boards and semiconductor devices. More specifically, the present invention relates to a wiring board inside which a capacitor is provided and a semiconductor device where a semiconductor element is mounted on the wiring board.
2. Description of the Related Art
Recently, in semiconductor elements, operational frequency has been increasing and consumption electric current is thus increased. Based on this, an operational voltage may be decreased due to the consumption electric current. Accordingly, in an electric power supply configured to supply electric power to a semiconductor element, a large change of electric current may be generated at a higher rate. It is extremely difficult to limit a voltage change of the electric power source due to change of the electric current within an allowable range of the electric power source.
Because of this, in a semiconductor device where a semiconductor element is mounted on a wiring board, plural capacitors are provided so that the change of the voltage of the electric power source is reduced. In other words, the change of the voltage of the electric power source is controlled by supplying an electric current from a chip capacitor to the semiconductor element by quick charging and discharging when an electric current has a high rate of change so that transitional change is made.
An example of a related art semiconductor device where the chip capacitor is provided is discussed with reference to FIG. 1 and FIG. 2. FIG. 1 is a cross-sectional view of an example of a related art semiconductor device. Referring to FIG. 1, a semiconductor device 300 includes a wiring board 500, a semiconductor element 400, solder bumps 410, and an underfill layer 420. A supporting body 510 is provided in a center part of the wiring board 500.
A first wiring layer 610a is formed on a first main surface 510a of the supporting board 510. A through-via hole 690 is formed in the supporting body 510 so as to pierce from the first main surface 510a to a second main surface 510b. The first wiring layer 610a is electrically connected to a fourth wiring layer 610b discussed below by way of the through-via hole 690. A first insulation layer 520a is formed so as to cover the first wiring layer 610a. A second wiring layer 620a is formed on the first insulation layer 520a. The first wiring layer 610a and the second wiring layer 620a are electrically connected to each other by way of a via-hole 520x piercing the first insulation layer 520a. 
A second insulation layer 530a is formed so as to cover the second wiring layer 620a. A third wiring layer 630a is formed on the second insulation layer 530a. The second wiring layer 620a and the third wiring layer 630a are electrically connected to each other by way of a via-hole 530x piercing the second insulation layer 530a. 
A solder resist film 550a having an opening part 550x is formed so as to cover the third wiring layer 630a. A part exposed from the opening part 550x of a solder resist film 550a of the third wiring layer 630a functions as an electrode terminal. In the following explanation, the part exposed from the opening part 550x of the solder resist film 550a of the third wiring layer 630a may be called an electrode terminal 630a. In the following explanation, a surface where the electrode terminal 630a is formed may be called a first main surface of the wiring board 500.
The fourth wiring layer 610b is formed on the second main surface 510b of the supporting body 510. A third insulation layer 520b is formed so as to cover the fourth wiring layer 610b. The fifth wiring layer 620b is formed on the third insulation layer 520b. The fourth wiring layer 610b and the fifth wiring layer 620a are electrically connected to each other by way of a via-hole 520y piercing the third insulation layer 520b. 
In addition, a fourth insulation layer 530b is formed so as to cover the fifth wiring layer 620b. A sixth wiring layer 630b is formed on the fourth insulation layer 530b. The fifth wiring layer 620b and the sixth wiring layer 630b are electrically connected to each other by way of a via-hole 530y piercing the fourth insulation layer 530b. 
In addition, a solder resist film 550b having an opening part 550y is formed so as to cover the sixth wiring layer 630b. A part exposed from the opening part 550y of the solder resist film 550b of the sixth wiring layer 630b functions as an electrode terminal. In the following explanation, the part exposed from the opening part 550y of the solder resist film 550b of the sixth wiring layer 630b may be called an electrode terminal 630b. In the following explanation, a surface where the electrode terminal 630b is formed may be called a second main surface of the wiring board 500.
A solder bump 680 is formed on a part of the electrode terminals 630b. The solder bump 680 functions as an outside connection terminal configured to be electrically connected to a corresponding terminal of a circuit wiring board when the semiconductor device 300 is mounted on the circuit wiring board. In addition, a chip capacitor 100 is mounted on a part of the electrode terminals 630b. Outside electrodes 260a and 260b of the chip capacitor 100 are electrically connected to the corresponding electrode terminals 630b. 
A semiconductor element 400 is mounted on the first main surface of the wiring board 500. The semiconductor element 400 has a structure where a semiconductor integrated circuit (not shown) or an electrode terminal (not shown) is formed on a thin-plate, shaped semiconductor wiring substrate (not shown) made of silicon or the like. A solder bump 410 is formed on an electrode terminal (not shown) of the semiconductor element 400.
The electrode terminal (not shown) of the semiconductor element 400 is electrically connected to corresponding electrode terminal 630a of the wiring board 500 by the solder bump 410. As a material of the solder bump 410, for example, an alloy of Sn and Cu, an alloy of Sn and Ag, an alloy of Sn, Ag, and Cu, and other alloys can be used. The underfill resin layer 420 is supplied between the semiconductor element 400 and the solder resist layer 550a of the wiring board 500.
FIG. 2 is an expanded cross-sectional view of the chip capacitor 100 shown in FIG. 1. Referring to FIG. 2, the chip capacitor 100 includes a dielectric body 210, plural inside electrodes 220a and 220b, and two outside electrodes 260a and 260b. 
The inside electrodes 220a and 220b are mutually stacked in a Z direction inside the dielectric body 210. The inside electrodes 220a and 220b are provided, in an area sandwiched by the outside electrodes 260a and 260b, substantially perpendicular to a surface 260a1 of the outside electrode 260a and a surface 260b1 of the outside electrode 260b facing each other. The inside electrodes 220a are connected to the outside electrode 260a. Plural inside electrodes 220b are connected to the outside electrode 260b. With this structure, a capacitor is formed between plural inside electrodes 220a and plural inside electrodes 220b. 
In order to reduce the change in the voltage of the electric power supply generated by the operational electric current of the semiconductor element 400, for example, plural chip capacitors 100 shown in FIG. 2 are connected between the electric power supply of the semiconductor element 400 and ground (GND). Since it is difficult to arrange the chip capacitor 100 in the vicinity of the semiconductor element 400, it is normal practice for the chip capacitor 100 to be mounted on the second main surface of the wiring board 500, which second main surface is opposite to the first main surface where the semiconductor element 400 is mounted.
In other words, the ground (GND) and the electric power supply of the semiconductor element 400 are extended to the second main surface of the wiring board 500, where the chip capacitor 100 is mounted, by way of the wiring layer, the via-hole, the through-via hole, and others. Approximately 30 through 50 chip capacitors 100 are mounted on the second main surface of the wiring board 500. Each of the chip capacitors 100 has, for example, a capacitance of approximately 1 μF through approximately 10 μF, so that the entire wiring board 500 has capacitance of approximately 50 μF through approximately 100 μF. As a result, it is possible to reduce the change of the voltage of the electric power supply.
In a case where the semiconductor chip 40 is operated at high frequency, in order to reduce the change of the voltage of the electric power supply by using the chip capacitor 100, it is preferable that the chip capacitor 100 be arranged in the vicinities of the ground (GND) and the electric power supply of the semiconductor chip 400 as close as possible. However, as discussed above, the chip capacitor 100 is connected, by way of the wiring layer, the via-hole, the through-via hole, and others, between the ground (GND) and the electric power supply of the semiconductor chip 400. Accordingly, it is difficult to reduce the inductance generated by the wiring layer or the like. Hence, when the semiconductor chip 400 is operated at the high frequency, there is a limitation to reducing the change of the voltage of the electric power supply by using the chip capacitor 100. This is because, if the inductance becomes high, corresponding to the change of the electric current at the high rate, the chip capacitor 100 charging and discharging is obstructed.
In order to solve such a problem, a technique has been suggested where a capacitor having a structure similar with that shown in FIG. 2 is formed inside the wiring board 500. By forming the capacitor inside the wiring board 500, it is possible to provide the capacitor near the semiconductor chip 400.
In this case, it is preferable that pitches of the outside electrodes of the capacitor be made equal to pitches of the electrode terminals 410 formed on the semiconductor chip 400 and the capacitor be formed right under the electrode terminal 410 corresponding to the ground (GND) and the electric power supply of the semiconductor chip 400. In addition, it is preferable that one of the outside electrodes of the capacitor be connected to the electrode terminal 410 corresponding to the electric power supply of the semiconductor chip 400 and another of the outside electrodes of the capacitor be connected to the electrode terminal 410 corresponding to the ground (GNU) of the semiconductor chip 400.
Thus, by forming the capacitor inside the wiring board 500 and connecting the capacitor as discussed above, it is possible to reduce the inductance generated by the wiring layer or the like.
In addition, it is possible to reduce the change of the voltage of the electric power supply more, compared to the conventional art, in a case where the semiconductor chip 400 is operated at high frequency. See Japanese Laid-Open Patent Application Publication No. 10-308565.
However, as miniaturization of the semiconductor device 300 or making the semiconductor device 300 thinner progresses, pitches of the electrode terminals 410 formed on the semiconductor chip 400 are made narrower. That is, high density of the electrode terminals 410 has been progressing. As the pitches of the electrode terminals 410 are narrower, it is necessary to make pitches of the outside electrodes of the capacitor to be connected to the electrode terminals 410 narrower.
In the related art capacitor, the inside electrodes are provided in a direction perpendicular to the thickness direction of the wiring board. Therefore, if the pitch of the outside electrodes of the capacitor is narrower, it may not be possible to make the area of the inside electrodes of the capacitor large. If the area of the inside electrodes of the capacitor is smaller, in proportion to that, the capacitance of the capacitor is smaller. Hence, it is difficult to reduce the change of the voltage of the electric power supply.